Not Applicable
Not Applicable
The present invention generally relates to mechanical polishing of a surface. More particularly, the present invention relates to composite fixed abrasive polishing pads and methods of use for mechanical polishing of the surface on a semiconductor substrate wafer.
Integrated circuits are typically constructed by depositing layers of predetermined materials to form circuit components on a wafer shaped semiconductor substrate. The formation of the circuit components in each layer generally produces a rough, or nonplanar, topography on the surface of the wafer. Nonplanar surfaces on the wafer can result in defects in subsequent circuit layers formed on the surface leading to flawed or improperly performing circuitry. Therefore, nonplanar surfaces must be made smooth, or planarized, to ensure a proper surface for the formation of subsequent layers of the integrated circuit.
Planarization of the outermost surface of the wafer is performed in two ways, locally over small regions of the wafers and globally over the entire surface. For example, a layer of oxide is typically deposited over the exposed circuit layer to provide an insulating layer for the circuit and to locally planarize regions by providing a continuous layer of material. A second layer of material is then deposited on top of the insulating layer to provide a surface that can be globally planarized without damaging the underlying circuitry. The second layer is generally composed of either an oxide or a polymer. Thick oxide layers can be deposited using conventional deposition techniques. Spin coating is a commonly used technique to form thick polymer layers on a wafer.
While deposition and spin coating techniques are useful in producing continuous uniform thickness layers, neither technique is particularly effective at producing a globally planar surface when applied to a nonplanar surface. As such, additional surface preparation is generally required prior to forming additional circuit layers on the wafer.
Other methods for globally planarizing the outermost surface of the wafer include chemical etching, press planarization and mechanical polishing, which includes chemical mechanical polishing, or planarization, (CMP). In chemical etching, the second layer is deposited over the preceding layers as described above and is chemically etched back to planarize the surface. The chemical etching technique is iterative in that following the etching step, if the surface was not sufficiently smooth, a new layer of polymer or oxide must be formed and subsequently etched back. This process is time consuming, lacks predictability due to its iterative nature, consumes significant amounts of oxides and/or polymers in the process, and generates significant amounts of waste products.
In global press planarization, a planar force is applied to press, or deform, the surface of the second layer to assume a planar topography. The obvious limitation to this technique is that a deformable material must be used to form the second layer.
Mechanical polishing of a surface is performed by mechanically abrading the surface generally with a polishing pad. Mechanical polishing can be performed either as a dry process (air lubricant) or a wet process (liquid lubricant).
In mechanical polishing, the wafer must be polished for a precise period of time to achieve a desired surface finish on the layer. If the wafer is not polished for a sufficient length of time, the desired finish will not be achieved. On the other hand, if the wafer is polished for a period of time longer than necessary, the continued polishing may begin to deteriorate the surface finish. The ability to control the time required to polish the surface of the wafer can greatly improve productivity by allowing for the automation of the process, increasing the yield of properly performing wafers, and reducing the number of quality control inspections necessary to maintain the process.
The size and concentration of the particles used to abrade the surface directly affect the resulting surface finish. If the particulate concentration is too low or the particle size too small, mechanical polishing will not proceed at a sufficient rate to achieve the desired polishing effect in the time provided. Conversely, if the particulate concentration is too high or the particles are too large, then the particulates will undesirably scratch the surface.
Polishing scratches are often a source of variability in the performance of the finished integrated circuit. Performance variability results from scratch induced problems, such as uneven interconnect metallization across a planarized surface and contamination effects due to the presence of voids formed or particles trapped in a layer as a result of the scratches.
In addition, mechanical polishing techniques often experience significant performance variations over time that further complicate the automated processing of the wafers. The degradation in performance is generally attributed to the changing characteristics of the polishing pad during processing. Changes in the polishing pad can result from particulates becoming lodged in or hardening on the surface of the pad, pad wear, or aging of the pad material.
Chemical mechanical polishing is a wet technique in which a chemically reactive polishing slurry is used in conjunction with a polishing pad to provide a synergistic combination of chemical reactions and wet mechanical abrasion to planarize the surface of the wafer. The polishing slurries used in the process are generally composed of an aqueous basic solution, such as aqueous potassium hydroxide (KOH), containing dispersed abrasive particles, such as silica or alumina. The polishing pads are typically composed of porous or fibrous materials, such as polyurethanes, that provide a relatively compliant surface in comparison to the wafer.
The benefits of performing both a chemical and a mechanical polishing of the surface are somewhat offset by the additional undesirable variations in the surface quality that can occur in CMP techniques. The additional variations generally result from imbalances that occur in the chemical and mechanical polishing rates. For example, if the chemical concentration is too low, the desired chemical reactions may not proceed at an appreciable enough rate to achieve the desired polishing effect. In contrast, if the chemical concentration is too high, etching of the surface may occur. Also, in CMP techniques, chemicals may become unevenly distributed in the pad resulting in further variations in the chemical polishing rate.
In addition, the chemicals that are needed to perform the CMP process are relatively expensive and are generally not recyclable. It is therefore desirable to minimize the amount of chemicals used in the process to reduce both the front end costs of purchasing and storing the chemicals and the back end costs of waste disposal.
Efforts have been made in the prior art to decrease the variability and increase the quality of the polish provided by CMP techniques. For instance, U.S. Pat. No. 5,421,769 to Schultz et al. discloses a noncircular polishing pad that attempts to compensate for uneven polishing that occurs as a result of the edges of the wafer traveling a greater distance across the polishing pad when a spinning polishing motion is used. U.S. Pat. No. 5,441,598 to Yu et al. discloses a polishing pad having a textured polishing surface that attempts to provide a surface that will more evenly polish wide and narrow depressions in the surface.
U.S. Pat. No. 5,287,663 to Pierce et al. discloses a polishing pad having a rigid layer opposite the polishing surface and a resilient layer adjacent to the rigid layer. The rigid layer imparts stability to the pad to prevent the unintended overpolishing, or dishing out, of material from between adjacent hard underlying features, while the resilient layer serves to redistribute any maldistribution of the polishing force. While the apparatuses and methods may provide a more planar surface by compensating for various features in the wafer, the inventions do not directly address the problem of overpolishing the wafer surface.
Other prior art efforts to minimize the uneven polishing of the wafer have focused on including additional material in the layers formed on the wafer to control overpolishing. U.S. Pat. Nos. 5,356,513 and 5,510,652 to Burke et al. and U.S. Pat. No. 5,516,729 to Dawson et al. all disclose the inclusion in the layers of additional material that is more or less susceptible to CMP than the material comprising the operative portion of the circuit.
The additional material included in the layer, known as a xe2x80x9cpolish stopxe2x80x9d, is used to prevent overpolishing of the wafer. However, polish stops do not overcome the problem of overpolishing, as discussed in the Dawson patent (col. 7, lines 18-59). Also, the procedures must be performed iteratively to obtain global planarization. The use of polish stops in the layer also increases the complexity of the manufacturing process and adds materials that are unnecessary to the end use of the circuit, both of which tend to increase the likelihood of flawed or improperly performing devices.
In view of these and other difficulties with prior art mechanical polishing techniques, there is a need for mechanical surface polishing methods and apparatuses that provide for a more generally applicable and predictable polishing technique.
In one embodiment, the present invention provides an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a motor. The polishing pad includes a polishing face, a first abrasive member having a first material and a first polishing surface, and a second member comprising a second material and a second surface. The first surface is capable of being positioned to extend beyond the second surface to provide a predetermined amount of abrasion to the wafer surface. The wafer support includes a support surface, and is disposed opposite to the pad. The motor operatively engages at least one of the polishing pad and the wafer support.
Another aspect of the present invention is an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a liquid source. The polishing pad includes a polishing face that has a first abrasive member comprising a first material and a first polishing surface, and a second member comprising a second material and a second surface. The first surface is capable of being positioned to extend beyond the second surface to provide a predetermined amount of abrasion to the wafer surface. The wafer support includes a support surface, and is disposed opposite to the pad. The liquid source is positioned to dispense a liquid between the polishing face and the support surface.
In another embodiment, the present invention provides an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a motor. The polishing pad includes a polishing face, an abrasive first member, and means for impeding abrasion of the surface by the first member. The wafer support includes a support surface, and is disposed opposite to the pad. The motor operatively engages at least one of the polishing pad and the wafer support.
Another aspect of the present invention provides an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a motor. The polishing pad includes a polishing face, and further includes a first member having a structurally degradable abrasive first material and a second member including means for impeding abrasion of the surface by the first member. The wafer support includes a support surface, and is disposed opposite to the pad such that the polishing face and the support surface are substantially parallel and can be brought within close proximity. The motor operatively engages at least one of the polishing pad and the wafer support.
In another embodiment, the present invention provides an apparatus for performing mechanical polishing of a semiconductor wafer surface that includes a polishing pad, a wafer support, and a motor. The polishing pad includes a polishing face, and further includes a first member comprising a structurally degradable abrasive first material and means for impeding abrasion of the surface by the first member. The wafer support includes a support surface, and is disposed opposite to the pad such that the polishing face and the support surface are substantially parallel and can be brought within close proximity. The motor operatively engages at least one of the polishing pad and the wafer support.